Solving computer organization and architecture midtrem

Solving computer organization and architecture midtrem Computer Architecture Mid-term. Dr Simon Ben-Avi. November 2015. Your name: (print, please; last, first) Your ID: Q1) CPU interface with Memory sub-system. A computer has an MDR (memory data register) of 16-bits. How many memory READ operations are necessary to transfer 16 bytes from memory into the CPU? Î 16 Ï 8 Ð 4 Ñ 2 Ò None of the previous Q2) General. Which of the following is/are true? I. Pure horizontal microinstructions have one bit assigned for every control line II. The connection between the main memory sub-system and the CPU has been called the “von Neumann ‘Bottleneck’ because instructions pass through this connection, slowing the C.P.U. III. General registers like “R3” are PIPO (parallel in-parallel out) registers Î I only Ï II only Ð III only Ñ I, II & III Ò None of the previous Q3) Flags. Remember the following: The Flags are set or reset individually on each occasion that the ALU is used. They are determined by the ALU to indicate the general nature of the result of the last operation. However it is the Control Unit which reads and uses the flags. What class(es) of instructions exist(s) for which, in order to execute them, the Control Unit must read these flags? Î Arithmetic Ï Logical Ð Conditional Ñ More than one of the above Ò None of the above Q4) Memory technologies. Any RAM memory has what kind of inputs? (Like the 74189 which we studied in class). Î Address Ï Data input lines Ð Data out Ñ All of the above. Ò More than one of the above but not all Q5) Basic knowledge, 1 bus architecture. What is or are true of CPU registers? I. Outputs of CPU registers are connected to its single bus via tri-state buffers II. Individual flip-flops in registers have all their clock inputs connected together III. Data may be presented at the inputs to these registers, but do not affect the output until the register is clocked Î I only Ï II only Ð III only Ñ I, II & III Ò None of the above or you cannot tell given this information Q6) Fundamental computer architecture. Look at the 3-bus architecture on the last page. Locate the numbers positioned around the diagram. Which three numbers are at the sources of the three busses? Î 1, 3 and 6 Ï 1, 3 and 4 Ð 2, 4 and 5 Ñ 2, 3 and 5 Ò None of the above or more than one of the above Q7) Basic concepts: negative numbers. Using a two’s complement representation with 6 bits total (including the sign bit), what is the correct representation of: -14 (minus 14)? Î 101110 Ï 110010 Ð 111000 Ñ 001110 Ò None of the above Q8) CPU control unit. A control unit uses a micro-coding scheme to control the CPU. Which of the following is/are true of the microcoding scheme? I. Variations of instructions must share a common control sequence otherwise the memory will grow too large. II. Variations within a particular instruction such as “ADD” include, or are caused by, different addressing modes used and varying operands. III. The IR feeds a look up table which determines where the micro-program instruction sequence begins. Î I, II and III Ï I only Ð II only Ñ III only Ò None of the above Q9) Basic knowledge. An excess 3, five bit code for POSITIVE integers is generated by taking a binary coded decimal number and adding three (3) to it. What is the maximum decimal number that can be represented using such a 5-bit code? â 32 ã 31 ä 29 å 28 æ None of the above Q10) CPU architecture. A control unit inside a three bus CPU begins to execute the instruction “SUB R0,R1". (Destination is the second operand). What thing(s) might the controller do first? What might it include in the first micro-step? Î Set ALU to “SUB” Ï Set multiplexer “A” to select input ‘0' Ð Clock ALU buffer register “A” Ñ More than one of the above, but not all. Ò All of the above (Î, Ï, & Ð) Q11) CPU control unit. What is/are true of “vertical” microprogrammed control versus “horizontal” micro-programmed control? (Remember that vertical micro-instructions use coded fields rather than a dedicated bit for each control line). I. The control signals often need extra gates to decode the vertical fields. II. There is one bit per control word for every control signal in every control word. III. Both vertical and horizontal schemes would use “stop bits” to avoid wasting space in the micro-control memory. Î I only Ï II only Ð III only Ñ More than one of the above Ò None of the above Q12) CPU control unit. The MFC ‘handshaking” signal is sent from memory to the CPU when the memory sub-system has finished the requested operation. Why is this signal necessary? I. The memory has a variable response time. II. The RAM may be going through a refresh cycle, and so it is or has been temporarily unavailable III. If reading, it can serve as a signal that the MDR can be safely clocked and the CPU can receive the data or instruction. Î I, II & III Ï I & II Ð I only Ñ II only Ò None of the above Q13) Basic Operation of CPU. Examine the one- and three-bus CPUs at the end of the paper. The control unit is shown without certain vital component content. What is missing? Î The MDR Ï A high-speed loadable counter Ð The MAR Ñ The PC Ò None of the above or more than one of the above Q14) Basic concepts: which of the following is/are true? I. Shifting a binary pattern one bit to the right divides the quantity by 2 II. The ALU carries out all arithmetic and logical operations, so therefore binary data must be copied into the CPU before any operation can take place III A CPU with a 16 bit MAR implies that the system uses 65,536 virtual memory addresses Î I & II Ï I, II & III Ð I & III Ñ II & III Ò None of the above Q15) Basic binary/hex conversion/addition. The unsigned sum of 16 16 positive numbers FACE and BADE is calculated in a computer which uses 16-bit registers. What will the flags NCZV be after the addition? NCZV (in order) will be ..... Î 0000 Ï 0100 Ð 0001 Ñ 0101 Ò None of the above. Hint: Flag N is set to 1 if the result is negative. Flag C is set to 1 if the result overflows by just 1 bit, i.e. there is a 17 bit result. Flag V is set to 1 if overflow happens, i.e. the result is more than 17 bits. Flag Z is set to 1 if the result is zero. Q16) Basic ALU in CPU. What is/are true of an ALU? I. The time between clock pulses to the ALU varies because the operations it carries out vary in the time taken to complete II. In the middle of an instruction, the output of the ALU may be nonsensical and transient III. MUL (multiply) is a higher order operator than ADD, so will operate faster through the ALU Î I only Ï II only Ð III only Ñ I & II Ò None of the above Q17) Basic assembler concepts. Literal values, such as the 102 in the instruction: “MOV #102, R2” are often placed interleaved with the compiler generated assembler program, immediately following the instruction in which they appear. During the execution of the instruction, what register in the CPU will point to the literal value (like the 102)? Î PC Ï MAR Ð MDR Ñ One of the general registers Ò None of the above Q18) Basic Architecture. What advantages does a two bus architecture have over a one bus configuration? I. A buffer at the ALU output is eliminated II. At all times, because there are two busses, two simultaneous transfers of data are possible III. Tri-state buffers are eliminated. Î I only Ï II only Ð III only Ñ I, II & III Ò None of the above Q19) Basic Architecture. Look at the one-bus architecture depicted on the last page. The interface to the main memory subsystem does not show any of the necessary control lines needed to successfully complete a transaction with main memory. To which unit in the CPU should such control signals be connected? Î The ALU Ï The MDR Ð The control unit Ñ It depends upon what signal it is. Ò None of the above Q20) Basic Architecture. A control sequence is to be generated from a ROM memory. The memory’s address lines are connected to a counter, which counts from 0 through 7. In the diagram below, the “x” axis is marked with the counter state. Fill in the content for the 16 address by 4-bit memory, and identify the content of word (or address) #4. Use the diagrams or templates after the last question to help you answer this. â 0A ã 1C ä 0C å 0E æ None of the alternatives Q21) Basic micro-instruction controlled CPU. When a control sequence terminates, this is usually indicated by what? â A stop bit ã An entry in a look-up table ä A control word of all zeros å More than one of the above æ None of the above. Q22) Basic CPU control. What things can be done to bring the size of a micro-control memory under control, from an impossible large size to a reasonable manageable one? I. Use “field encoded” vertical micro-instructions II. Implement the ability to skip portions of a “master” microinstruction sequence (to accommodate variations) III. Allocate a fixed amount of space for each micro-instruction sequence. â I only ã I and II ä I, II and III å II and III æ None of the above Q23) Basic CPU Concepts. What features of the generic 2-bus architecture make it ineffective in significantly speeding up the operation of the CPU? I. The bus tie causes the two independent busses to act as one most of the time II. Tri-state buffers, used in order to turn the busses around, continue to be necessary and slow overall operation speed. III. The control unit has significantly many more control signals to generate â I only ã II only ä III only å I & II æ None of the above choices is correct Q24) Challenge. Imagine a simpler CPU without general registers, but with, instead, a push-down stack of registers. In other words, R0 though Rx become a stack where your instructions are to operate. “ADD” will take the top two values from the stack, add them, and push back the result, for instance. Example: a computer like this would accept a sequence such as: load A ;puts memory variable “A” into the stack at the top load B ;puts memory variable “B” into the stack, at the top, ;also pushing “A” down add ; needs no arguments. Top two values are removed ; and their sum pushed back write C ;remove top of stack and write to memory in a ;user variable called “C” You can see the similarity between this, and a high-level statement such as “C = A + B”. Which of the following sequences will accomplish “D = A + B + C”? Ø Load A Ù Load A Ú Load A Load B Load B Load B Load C Add Load C Add Load C Add Add Add Write D Write D Write D å Both Ø and Ù æ None of the above alternatives Q25) Basic knowledge of Complements. A fixed 6-bit system of 2's-complement integers is used in a computer. The CPU is asked to calculate “ -a +(-2*a)”.What is the maximum value of “a” that can be accommodated during this calculation without the ALU setting the oVerflow flag, V? â 1 ã 2 ä 3 å 4 æ None of the previous alternatives Scoring: +1 for a correct answer -¼ for an incorrect answer 0 for no answer to a question Diagrams for question 20 ....... Put S0 in the first column, S1 in the second column, S2 in the third and S3 in the last. Three bus architecture is above. One bus architecture is below.